In the context of circuit design, it is commonplace to evaluate the data communication pathways interconnecting various circuits within a system. Oftentimes, in performing such tests, it is necessary to measure the span of time between two logic level transitions within a signal (or between two transitions in different signals) that has propagated through a communication pathway to be evaluated. For example, in performing such an evaluation, one may wish to measure the span of time between the second rising edge and fourth rising edge in a data signal that has propagated through a communication pathway under test.
FIG. 1 depicts an exemplary system for performing such a measurement. As can be seen from FIG. 1, the exemplary system includes a limiting amplifier 100 that receives a signal 102 that has propagated through a pathway (not depicted in FIG. 1) to be evaluated. The limiting amplifier 100 generates at its output 104 an amplified, isolated output signal that includes the same data transitions as those exhibited by the input signal 102. Of course, the limiting amplifier 100 exhibits a small delay period, c, meaning that a logic level transition occurring at time t0 at the input of the limiting amplifier 100 is witnessed at time t0+c at the output 104 thereof.
The output of the limiting amplifier 100 is delivered to a first edge selection system 106, a second edge selection system 108, and an arming circuit 110. The first edge selection system 106 includes an amplifier 112, which functions in the same manner as the aforementioned limiting amplifier 100. Thus, the output of the amplifier 112 is essentially an isolated and slightly delayed replica of the input signal 102. The output of the amplifier 112 is delivered to an edge selection circuit 114. The edge selection circuit 114 is composed of flip flops, counters, and other combinatorial logic arrangements. The edge selection circuit 114 is configured to select a particular logic level transition (also referred to herein as an “edge” or as a “transition”) from the output data signal 102, and to deliver the selected edge to a time interval measurement system 116. Thus, for example, the edge selection circuit 114 may select the second rising edge from the signal 102. Per such a scenario, the arming circuit 110 instructs the edge selection circuit 114 when to begin counting rising edges within the data signal 102, and upon observation of the second rising edge, the edge selection circuitry 114 delivers that edge to the time interval measurement system 116. The second edge selection system 108 (comprised of amplifier 117 and edge selection circuitry 118) works in an identical manner, with the notable exception that it may select a different edge than is selected by the first edge selection system 106 (it may select the same edge, as well). The time interval measurement system 116 measures the interval of time between the two edges selected by the first and second edge selection systems 106 and 108.
FIGS. 2A-2C depict the behavior of the system of FIG. 1, assuming that the second and fourth rising edges have been selected for measurement. FIG. 2A depicts the incoming data signal 102 of FIG. 1. The second rising edge in the incoming data signal 102 is identified by reference numeral 200, and the fourth rising edge is identified by reference numeral 202. As can be seen, an ideal measurement of the interval of time between these two edges yields a quantity of I.
It should be noted that for the purpose of discussion of the subject matter herein, the logic level transitions are depicted and described as vertical “edges,” such that a transition from a logic level low to a logic level high, or vice versa, is described as occurring instantly. Of course, a logic level transition occurring in an actual system occurs over a span of time. The edges depicted herein can be thought of as occurring at the instant in time at which the signal crosses a threshold (e.g., voltage threshold) that defines the distinction between a logical “0” from a logical “1.”
FIG. 2B depicts the behavior exhibited at the output of the first edge selection circuit 114. The depiction is presented as a Cartesian plane, with time on the x-axis and voltage on the y-axis. Notably, time=K at the origin of the Cartesian plane. The term K is equal to the propagation delay of the signal 102 through the amplifiers 100 and 112. Thus, assuming that the first edge selection circuit 114 exhibited no propagation delay, the rising edge 200′ (depicted in FIG. 2B) at the output thereof would appear vertically aligned with the rising edge 200 of the data signal (depicted in FIG. 2A). However, as can be seen from FIG. 2B, the first edge selection circuit 114 signal exhibits a propagation delay D1. As can be seen from FIG. 2C, the second edge selection circuit 118 exhibits a propagation delay D2. Thus, the interval between the second leading edge 200 and fourth leading edge 202, as measured by the interval measurement system 116, is (I−D1+D2), instead of I.
As shown in FIG. 3, the propagation delay exhibited by an edge selection circuit 114 and/or 118 is a function of, amongst other variables, the frequency content of the signal propagating through the selection circuit. Thus, the propagation delays D1 and D2 constantly change, and simple addition/subtraction of a constant cannot achieve the end goal of correcting the measurement generated by the interval measurement system 116.
From the foregoing, it is evident that there exists a need by which distortions, such as frequency-dependent distortion (and other mechanisms, e.g., thermal), of interval measurements may be reduced.